Not to connect memory signals if only local RAM.

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lannylian
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lannylianApr 8 2015, 2:25 PM
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rLEGUPfd02d62da9d9: II reduced to 1 w/ local ram load latency set to 0
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Description

Not to connect memory signals if only local RAM.

rLEGUP0fc36cc2296e

llvm/lib/Target/Verilog/GenerateRTL.cpp

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