Fixed the simulation error when a verilog file include other file

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Authored
fort
Committed
fortApr 12 2015, 12:43 PM
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rLEGUPec67a701f758: Changed all local board overrides to use set_project instead of set_board
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Description

Fixed the simulation error when a verilog file include other file

If a verilog file includes another file, which are both in the
simulation's submodules directory, there used to be in error when
compiling in ModelSim. This change fixes the ModelSim scripts to use the
submodules directory as an include directory.

rLEGUP0fd7541d6fef

examples/scripts/simulation/run_sim_nowave.tcl

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examples/scripts/simulation/run_sim_wave.tcl

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