Change Ram latency to support 0 latency load.

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lannylian
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lannylianApr 8 2015, 11:36 AM
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rLEGUP3d7a118f4999: pipelined FIR exampl with streaming testbench.
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Description

Change Ram latency to support 0 latency load.

Also add error messages if wrong latency parameter is used.

rLEGUP527edb1a4a6f

llvm/lib/Target/Verilog/VerilogWriter.cpp

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llvm/lib/Target/Verilog/VerilogWriter.h

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