Merge branch 'llvm-3.5' of legup.org:legup into llvm-3.5

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Authored
fort
Committed
fortApr 13 2015, 12:47 AM
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rLEGUPf1cd1b04e31d: Re-add tiger sw pass for profiling. · rLEGUP3d6182a9fb3d: Added performance counter to the ip directory.
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Description

Merge branch 'llvm-3.5' of legup.org:legup into llvm-3.5

Conflicts:
examples/Makefile.common

Merged Changes

CommitRevisionAuthor/CommitterDetailsDateTime
rLEGUPf1cd1b04e31dbains
Re-add tiger sw pass for profiling. 
Apr 12 201511:12 PM
rLEGUPc6f36ad5e3f2bains
Remove accidentally added temp file. 
Apr 12 201510:33 PM
rLEGUPb768ddde9994bains
Change a couple linker commands that I missed before. 
Apr 12 201510:30 PM
rLEGUPe32071f8f358bains
Remove sed command that breaks buildbot. 
Apr 12 201510:15 PM
rLEGUP3ebb02c48090bains
Add system for CycloneIIAuto to fix Buildbot. 
Apr 12 20159:33 PM
rLEGUP0df0f0921d43bains
Remove altera_libs dependancies from tiger_DE4. 
Apr 12 20159:05 PM
rLEGUP19b9d68fa73fbains
Make sure output directory is created. 
Apr 12 20159:01 PM
rLEGUP45476987db7cbains
Change all mips link targets to use same linker script. 
Apr 12 20158:49 PM
rLEGUP39be68b0aaf3bains
Remove altera_lib includes. 
Apr 12 20158:46 PM
rLEGUP3a494f9cc3cebains
Add missing parameters for OVERRIDE_BOARD=DE1-SoC 
Apr 12 20157:49 PM

Changes (223)

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HistoryBrowseModifiedexamples/lib/legup.exp
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HistoryBrowseModifiedllvm/lib/Target/Verilog/LegupConfig.cpp
HistoryBrowseModifiedswtools/mips/prog_link.ld
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HistoryBrowseModifiedtiger/processor/tiger_DE4/tiger.v

rLEGUP7e724a3ff8ed

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup.tcl

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system.qsys

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system.sopcinfo

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/legup_system.qip

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/legup_system.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_packets_to_master.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_sc_fifo.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_st_bytes_to_packets.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_st_clock_crosser.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_st_idle_inserter.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_st_idle_remover.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_st_jtag_interface.sdc

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_st_jtag_interface.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_st_packets_to_bytes.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_avalon_st_pipeline_base.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_jtag_dc_streaming.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_jtag_sld_node.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_jtag_streaming.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_address_alignment.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_arbitrator.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_burst_adapter.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_burst_uncompressor.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_master_agent.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_master_translator.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_slave_agent.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_slave_translator.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_traffic_limiter.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_merlin_width_adapter.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_pli_streaming.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_reset_controller.sdc

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_reset_controller.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/altera_reset_synchronizer.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_dm_wt_cache.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_simple_cache.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_JTAG_UART.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_JTAG_to_FPGA_Bridge.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_JTAG_to_FPGA_Bridge_b2p_adapter.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_JTAG_to_FPGA_Bridge_p2b_adapter.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_JTAG_to_FPGA_Bridge_timing_adt.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_Onchip_SRAM.hex

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_Onchip_SRAM.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_SDRAM.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_SDRAM_test_component.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_UART.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_addr_router.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_addr_router_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_addr_router_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_addr_router_003.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_demux.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_demux_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_demux_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_demux_003.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_mux.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_mux_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_mux_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_mux_003.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_cmd_xbar_mux_004.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_id_router.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_id_router_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_id_router_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_id_router_003.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_id_router_004.sv

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boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_rsp_xbar_demux.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_rsp_xbar_demux_001.sv

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boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_rsp_xbar_mux.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/legup_system_rsp_xbar_mux_001.sv

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boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/submodules/tiger_icache_parameters.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/tiger_alu.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/tiger_avalon.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/tiger_avalon_im.v

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boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/synthesis/submodules/tiger_icache_av_1port.v

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boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system.ipx

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb.html

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb.qsys

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/legup_system_tb.v

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boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_avalon_st_bytes_to_packets.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_avalon_st_clock_crosser.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_avalon_st_idle_inserter.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_avalon_st_idle_remover.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_avalon_st_jtag_interface.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_avalon_st_packets_to_bytes.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_avalon_st_pipeline_base.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_conduit_bfm.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_jtag_dc_streaming.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_jtag_sld_node.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_jtag_streaming.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_address_alignment.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_arbitrator.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_burst_adapter.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_master_agent.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_master_translator.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_slave_agent.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_slave_translator.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_traffic_limiter.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_merlin_width_adapter.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_pli_streaming.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_reset_controller.sdc

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_reset_controller.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_reset_synchronizer.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/altera_sdram_partner_module.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_dm_wt_cache.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_simple_cache.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_JTAG_UART.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_JTAG_to_FPGA_Bridge.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_JTAG_to_FPGA_Bridge_b2p_adapter.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_JTAG_to_FPGA_Bridge_p2b_adapter.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_JTAG_to_FPGA_Bridge_timing_adt.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_Onchip_SRAM.hex

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_Onchip_SRAM.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_SDRAM.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_SDRAM_test_component.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_UART.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_addr_router.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_addr_router_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_addr_router_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_cmd_xbar_demux.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_cmd_xbar_demux_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_cmd_xbar_demux_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_cmd_xbar_mux.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_cmd_xbar_mux_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_cmd_xbar_mux_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_cmd_xbar_mux_003.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_id_router.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_id_router_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_id_router_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_id_router_003.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_id_router_004.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_rsp_xbar_demux.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_rsp_xbar_demux_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_rsp_xbar_demux_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_rsp_xbar_demux_003.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_rsp_xbar_mux.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_rsp_xbar_mux_001.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/legup_system_rsp_xbar_mux_002.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_alu.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_avalon.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_avalon_im.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_branch.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_decode.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_decoder.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_defines.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_div.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_divu.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_execute.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_fetch.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_ff.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_icache.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_icache_av_1port.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_icache_memory.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_icache_mux_param.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_icache_parameters.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_memoryaccess.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_mult.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_multu.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_shifter.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_stalllogic.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_tiger.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_top.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/tiger_writeback.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/true_dual_port_ram_single_clock.v

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/legup_system/testbench/legup_system_tb/simulation/submodules/verbosity_pkg.sv

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/scripts/Makefile

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/scripts/gen_legup_system.tcl

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/top.qpf

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/top.qsf

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/top.sdc

boards/CycloneII/CycloneIIAuto/Tiger_SDRAM/top.v

examples/Makefile.ancillary

examples/Makefile.aux

examples/Makefile.common

examples/Makefile.config

examples/lib/legup.exp

ip/altera_libs/stratixiii_atoms.v

llvm/lib/Target/Verilog/LegupConfig.cpp

swtools/mips/prog_link.ld

tiger/processor/tiger_DE2/tiger.v

tiger/processor/tiger_DE4/tiger.v

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