Fix longevity reg going to dataport of store inst.

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lannylian
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lannylianApr 10 2015, 12:58 PM
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rLEGUP83a0fc9e114b: Update FIR: pipeline loop in C, w/ unroll pass.
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streaming_support
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Description

Fix longevity reg going to dataport of store inst.

This commit is for function pipeline.
If a datapath register is directly connected to the dataport of a store inst,
we add a wire to bridge between register and the dataport. Then the longevity
register code can detect if the input register is longevity, meaning it is
defined at a state more than II cycles earlier than it is used by the dataport.

rLEGUP8e5060e98caa

llvm/lib/Target/Verilog/GenerateRTL.cpp

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llvm/lib/Target/Verilog/GenerateRTL.h

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