Changing the legup.tcl to use set_project instead of set_board and set_family

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Audit Required
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Restricted Project
H2 Triggered Audit
Authored
fort
Committed
fortApr 12 2015, 12:34 PM
Parents
rLEGUP9c030a82a434: Added the simulation atoms for Cyclone IV and V and Stratix V.
Branches
Unknown
Tags
Unknown
Subscribers
None
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Description

Changing the legup.tcl to use set_project instead of set_board and set_family

set_project sources the characterization file specific to each board. This file
in turn sources the characterization file for the appropriate device family.
set_project also sources the legup.tcl file specific to the project.

Added a new tcl command that sets the output path that is currently used by the
sw-only flow. Soon to be used by the hybrid flow. Also, hopefully to be used by
the hw-only flow.

Changes (35)

HistoryBrowseChangePath
HistoryBrowseModifiedboards/CycloneII/CycloneII.tcl
HistoryBrowseAddedboards/CycloneII/CycloneIIAuto/CycloneIIAuto.tcl
HistoryBrowseModifiedboards/CycloneII/DE2/DE2.tcl
HistoryBrowseModifiedboards/CycloneIV/CycloneIV.tcl
HistoryBrowseAddedboards/CycloneIV/DE0-Nano/
HistoryBrowseAddedboards/CycloneIV/DE0-Nano/DE0-Nano.tcl
HistoryBrowseAddedboards/CycloneIV/DE0-Nano/Tiger_SDRAM/
HistoryBrowseAddedboards/CycloneIV/DE0-Nano/Tiger_SDRAM/legup.tcl
HistoryBrowseAddedboards/CycloneIV/DE2-115/DE2-115.tcl
HistoryBrowseAddedboards/CycloneIV/DE2-115/Tiger_SDRAM/
HistoryBrowseAddedboards/CycloneIV/DE2-115/Tiger_SDRAM/legup.tcl
HistoryBrowseModifiedboards/CycloneV/CycloneV.tcl
HistoryBrowseAddedboards/CycloneV/DE1-SoC/DE1-SoC.tcl
HistoryBrowseAddedboards/CycloneV/DE1-SoC/Tiger_SDRAM/
HistoryBrowseAddedboards/CycloneV/DE1-SoC/Tiger_SDRAM/legup.tcl
HistoryBrowseDeletedboards/StratixIV/DE4
HistoryBrowseAddedboards/StratixIV/DE4-230/
HistoryBrowseAddedboards/StratixIV/DE4-230/DE4-230.tcl
HistoryBrowseAddedboards/StratixIV/DE4-230/Tiger_DDR2/
HistoryBrowseAddedboards/StratixIV/DE4-230/Tiger_DDR2/legup.tcl
HistoryBrowseAddedboards/StratixIV/DE4-530/
HistoryBrowseAddedboards/StratixIV/DE4-530/DE4-530.tcl
HistoryBrowseAddedboards/StratixIV/DE4-530/Tiger_DDR2/
HistoryBrowseAddedboards/StratixIV/DE4-530/Tiger_DDR2/legup.tcl
HistoryBrowseDeletedboards/StratixIV/DE4/DE4.qsf
HistoryBrowseDeletedboards/StratixIV/DE4/top.v
HistoryBrowseModifiedboards/StratixIV/StratixIV.tcl
HistoryBrowseAddedboards/StratixV/DE5-Net/DE5-Net.tcl
HistoryBrowseAddedboards/StratixV/DE5-Net/Tiger_DDR3/
HistoryBrowseAddedboards/StratixV/DE5-Net/Tiger_DDR3/legup.tcl
HistoryBrowseModifiedboards/StratixV/StratixV.tcl
HistoryBrowseModifiedexamples/legup.tcl
HistoryBrowseModifiedllvm/lib/Target/Verilog/LegupConfig.cpp
HistoryBrowseModifiedllvm/lib/Target/Verilog/LegupConfig.h
HistoryBrowseModifiedllvm/lib/Target/Verilog/LegupTcl.cpp

rLEGUPeb6c09cef3c5

boards/CycloneII/CycloneII.tcl

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boards/CycloneII/CycloneIIAuto/CycloneIIAuto.tcl

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boards/CycloneII/DE2/DE2.tcl

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boards/CycloneIV/CycloneIV.tcl

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boards/CycloneIV/DE0-Nano/DE0-Nano.tcl

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boards/CycloneIV/DE0-Nano/Tiger_SDRAM/legup.tcl

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boards/CycloneIV/DE2-115/DE2-115.tcl

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boards/CycloneIV/DE2-115/Tiger_SDRAM/legup.tcl

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boards/CycloneV/CycloneV.tcl

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boards/CycloneV/DE1-SoC/DE1-SoC.tcl

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boards/CycloneV/DE1-SoC/Tiger_SDRAM/legup.tcl

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boards/StratixIV/DE4

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boards/StratixIV/DE4-230/DE4-230.tcl

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boards/StratixIV/DE4-230/Tiger_DDR2/legup.tcl

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boards/StratixIV/DE4-530/DE4-530.tcl

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boards/StratixIV/DE4-530/Tiger_DDR2/legup.tcl

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boards/StratixIV/DE4/DE4.qsf

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boards/StratixIV/DE4/top.v

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boards/StratixIV/StratixIV.tcl

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boards/StratixV/DE5-Net/DE5-Net.tcl

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boards/StratixV/DE5-Net/Tiger_DDR3/legup.tcl

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boards/StratixV/StratixV.tcl

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examples/legup.tcl

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llvm/lib/Target/Verilog/LegupConfig.cpp

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llvm/lib/Target/Verilog/LegupConfig.h

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llvm/lib/Target/Verilog/LegupTcl.cpp

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