Mips1 With Llvm 3.5

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bains
Last Updated
977 Days Ago
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Changes to get MIPS1 compatible assembly with LLVM 3.5

The MIPS backend in LLVM 3.5 does not support the mips1 ISA. The closest one is mips32. Since there are a few differences between mips1 and mips32, a few changes are made to both the LLVM backend and the produced assembly code in order to make the mips32 assembly compatible with our Tiger MIPS processor (which is mips1).

Conditional Move

MIPS1 does not support the conditional move instructions movn and movz.

replace:

movz $1, $2, $3

with:

 bne  $3, $zero, $mytag###                                                    
 add  $1, $2, $zero                                                           
mytag###:

replace:

movn $1, $2, $3

with:

 beq  $3, $zero, $mytag###                                                    
 add  $1, $2, $zero                                                           
mytag###:

NOP After Load

replace:

lw $1 $2

with:

lw $1 $2
nop

MUL Instruction

replace:

mul  $1, $2, $3

with:

multu $2, $3                                                                 
mflo  $1

ADDE, SUBE Instructions

Disable ADDE and SUBE instructions in MipsSEISelLowering.cpp

Delay Slot Filling

Default to not fill delay slots in MipsAsmPrinter.cpp

See: rLEGUP0dea82917a8e: LLVM 3.5 update: modify Mips target so it produces code more compatible with…

Listing MIPS Instructions

The following command can be used to get a list of all assembly instructions used in an assembly file:

awk '{print $1}' <YOUR_ASSEMBLY_FILE>.s | sort | uniq | grep -v "[:|^.|#]"